The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
Many electronic circuits, such as processors, use power gating to turn off circuit blocks that are not in use, thereby saving power. The circuit may include a sleep transistor coupled between the power supply and the circuit block and/or between the ground terminal and the circuit block to selectively disconnect the circuit block. In advanced metal-oxide-semiconductor field effect transistor (MOSFET) processes with thin oxide thickness (e.g., small Tox), and/or in circuit conditions with large drain-source voltage, gate-induced drain leakage (GIDL) current is a significant leakage component of total standby current.